SCC: A Flexible Architecture for Many-Core Platform Research
Computing in science & engineering (Print)
The Single-chip Cloud Computer (SCC) experimental processor by Intel Labs is a "concept vehicle" aimed at scaling future multicore processors and serving as a software research platform. To mitigate the power wall's effect on CPU performance, the industry has switched to multicore designs in virtually all mainstream application markets within the last five years. According to Moore's law, increasing transistor integration will let us build many-core designs to further improve energy efficiency
... energy efficiency of logic operations. 1 Intel Labs' Single-chip Cloud Computer (SCC) experimental processor, 2 a 48-core concept vehicle incorporating technologies intended to scale multicore processors to 100 cores and beyond, was also created as a platform for many-core software research. It exposes many hardware "knobs" to system software and applications to foster outsidethe-box experiments for new options in how to organize and coordinate hardware and software. We'll be able to leverage many-core efficiency only if we can match the parallelism in the hardware architecture with concurrency in the software stack. Here, we'll highlight SCC's capabilities for flexible use of on-die and off-die resources for efficient synchronization and communication among cores. These capabilities expand the design space for exploration of an Intel Architecture (IA) platform significantly. As the "MARC: The Many-Core Applications Research Community" sidebar describes, the synergies within Intel's MARC program underpin SCC's usefulness as a flexible research tool for assessing the possible software and hardware features of future many-core architectures. SCC's Top-Level Architecture As Figure 1 shows, SCC is organized in 24 tiles connected by a 6 × 4 rectangular 2D mesh topology. 2,3 Each tile consists of two IA32 cores based on P54C Intel Pentium® in-order execution cores. Each tile is connected to a mesh router. The 48 cores can communicate over the on-die network using a message-passing architecture that allows data sharing with software-maintained memory consistency. Four independent double data rate type three (DDR3) memory channels provide main memory capacity. The processor is connected subsystem, validated the silicon and hardware platform, and implemented the software framework for SCC. His research interests include processor architectures, embedded systems, and FPGA prototyping. Konow received a diploma degree in electrical engineering from the Braunschweig University of Technology and is the recipient of two Intel Achievement Awards. Contact him at email@example.com. Michael Riepen is a senior research engineer at Intel Labs Braunschweig, where he worked on SCC pre-and post-silicon validation and created SCC's management software framework. His research interests include many-core programmability, validation methodologies, and exascale computing. Riepen has an MSc in computer science from the University of Applied Sciences Wedel, Germany, and is recipient of an Intel Achievement Award. Contact him at firstname.lastname@example.org. The Single-chip Cloud Computer (SCC) experimental processor is a 48core "concept vehicle" created by Intel Labs incorporating technologies intended to scale future multicore processors and to serve as a platform for many-core software research.