Yield analysis of a novel wafer manipulation method in 3D stacking
2013 IEEE International 3D Systems Integration Conference (3DIC)
Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC, including heterogeneous integration, reduced delay and power dissipation, smaller chip area, etc. Wafer-on-wafer stacking is attractive for 3D IC fabrication, but it suffers from low compound yield of the stacked chips. To improve the compound yield, a novel manipulation of sector symmetry and cut (SSC) is proposed. In this method, wafers with rotational symmetry are cut into identical sectors, which
... al sectors, which are then used to replenish the repositories. The SSC method is combined with best-pair matching algorithm for compound yield evaluation. Simulation results show that: 1) For wafers with radially clustered defects, plain rotation of wafers offers trivial benefits in yield. 2) SSC shows significantly higher yield than that for existing methods under various conditions. The advantage becomes even more obvious with increased repository size, larger number of stacked layers, and the decreased wafer yield. 3) A cut number of 4 is always optimal in increasing the final production size of good 3D ICs.