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ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
ATPG tools generate test vectors assuming zero delay model for logic gates. In reality, however, gates have finite rise and fall delays that are dependent on process, voltage, and temperature variations across different dies on a wafer and within a die. A test engineer must verify the vectors for timing correctness before they are handed off to the product engineer. Currently, validation of tests is done using dynamic simulation of the circuit using the test vectors. A test vector isdoi:10.1109/iccad.2003.159762 fatcat:4g732uhzqvfztmipooghbf2ngu