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Conventional processor fault tolerance based on time/space redundancy is robust but prohibitively expensive for commodity processors. This paper explores an unconventional approach to designing a cost-effective fault-tolerant superscalar processor. The idea is to engage a regimen of microarchitecture-level fault checks. A few simple microarchitecture-level fault checks can detect many arbitrary faults in large units, by observing microarchitecture-level behavior and anomalies in this behavior.doi:10.1109/dsn.2008.4630065 dblp:conf/dsn/ReddyR08 fatcat:unq3sfknhjbgrnmpcbkjeqjh3y