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A study of pipeline architectures for high-speed synchronous DRAMs
IEEE Journal of Solid-State Circuits
The performances of SDRAM's with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. The analysis shows that the cycle time of the conventional pipeline structures cannot be reduced because of its difficulty in distributing the access time evenly to each pipeline stage of the column address access path. On the contrary, the wave pipeline architecture can make the access path evenly divided and can increasedoi:10.1109/4.634671 fatcat:pfai3bvuwbfmthgx3mofonaf5q