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13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology
2014
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Intel, Hillsboro, OR CMOS technology scaling continues to drive higher levels of integration in VLSI design, which adds more compute engines on a die. To meet the overall performance-scaling needs, high-speed and high-bandwidth memory is becoming increasingly important. Conventional VLSI systems often rely on ondie SRAMs to address the performance gap between CPU and main memory, DRAM. However, with the rapid growth in capacity needs for high-performance memory, SRAM is not always sufficient to
doi:10.1109/isscc.2014.6757412
dblp:conf/isscc/HamzaogluABGLLM14
fatcat:l23vhgwz65gepmlmkv5aqu3dzi