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Oblivious algorithms for multicores and network of processors
2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)
We address the design of parallel algorithms that are oblivious to machine parameters for two dominant machine configurations: the chip multiprocessor (or multicore) and the network of processors. First, and of independent interest, we propose HM, a hierarchical multi-level caching model for multicores, and we propose a multicore-oblivious approach to algorithms and schedulers for HM. We instantiate this approach with provably efficient multicore-oblivious algorithms for matrix and prefix sumdoi:10.1109/ipdps.2010.5470354 dblp:conf/ipps/ChowdhurySBR10 fatcat:wiynwlarl5cw7c5c7mgso5yzly