Specification Enforcing Refinement for Convertibility Verification

Partha Roop, Alain Girault, Roopak Sinha, Gregor Goessler
2009 2009 Ninth International Conference on Application of Concurrency to System Design  
Protocol conversion deals with the automatic synthesis of an additional component or glue logic, often referred to as an adaptor or an interface, to bridge mismatches between interacting components, often referred to as protocols. A formal solution, called convertibility verification, has been recently proposed, which produces such a glue logic, termed as a converter, so that the parallel composition of the protocols and the converter also satisfies some desired specification. A converter is
more » ... ponsible for bridging different kinds of mismatches such as control, data, and clock mismatches. Mismatches are usually removed by the converter (similar to controllers in supervisory control of Discrete Event Systems (DES)) by disabling undesirable paths in the protocol composition. This paper formulates a generalization of this convertibility verification problem, by using a new refinement called specification enforcing refinement (SER) between a protocol composition and a desired specification. The existence of such a refinement is shown to be a necessary and sufficient condition for the existence of suitable a converter. We also propose an approach to automatically synthesize a converter if a SER refinement relation exists. The proposed converter is capable of the usual disabling actions to remove undesirable paths in the protocol composition. In addition, the converter can perform forcing actions when disabling alone fails to find a converter to satisfy the desired specification. Forcing allows the generation of control inputs in one protocol that are not provided by the other protocol. Forcing induces state-based hiding, an operation not achievable using DES control theory. Index Terms-protocol conversion, forced simulation. Partha S Roop and Roopak Sinha are respectively senior lecturer and postdoctoral fellow at the
doi:10.1109/acsd.2009.25 dblp:conf/acsd/RoopGSG09 fatcat:22xxts7gxjen7inyttavhwlwh4