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Proceedings of the conference on Design, automation and test in Europe - DATE '00
This paper presents a new delay minimization and technology mapping algorithm for two-level structures (TLS) implemented using clock-delayed (CD) domino logic. We take advantage of CD domino's high-speed, large fan-in NOR and OR gates to increase the speed of a circuit by partial collapsing. The algorithm is delay-driven and the delays are obtained from a characterized CD domino library. The results on eight combinational MCNC benchmark circuits show an average speed improvement of 89% for CDdoi:10.1145/343647.343781 fatcat:b73ielprwneilicxcqctrrrzzq