Design and Analysis of Phase Locked Loop and Performance Parameters

Nilesh D. Patel, Gunjankumar R. Modi, Priyesh P. Gandhi, Amisha P. Naik P. Naik
2017 International Journal of Microelectronics Engineering  
In this paper, we are present design and analysis of PLL, which is simulated in CMOS 0.18μm technology. The digital phase locked loop achieves locking within about 100 reference clock cycles. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart.In this PLL circuit successfully achieved 1.55GHz frequency. Jitter is 1.09ns achieved is very less. Also achieve low phase noise -98.5827 at 1MHz Frequency.
doi:10.5121/ijme.2017.3301 fatcat:flwjodubhre5rlvtncn7v6dege