An 8-bit 150-MHz CMOS A/D converter

Yun-Ti Wang, B. Razavi
2000 IEEE Journal of Solid-State Circuits  
This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers to achieve a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining scheme incorporates distributed sampling between the stages so as to
more » ... ax the linearity-speed tradeoffs in the sample-and-hold circuits. A clock edge reassignment technique is also introduced that suppresses timing mismatches in interleaved systems, and a punctured interpolation method is proposed that reduces the integral nonlinearity error with negligible speed or power penalty. Fabricated in a 0.6-µm CMOS technology, the converter achieves differential and integral nonlinearities of 0.62 and 1.24 LSB, respectively, and a signal-to-(noise + distortion) ratio of 43.7 dB at a sampling rate of 150 MHz. The circuit draws 395 mW from a 3.3-V supply and occupies an area of 1.2 × 1.5 mm 2 .
doi:10.1109/4.826812 fatcat:sqogtfe3tzbjdeblq6x3ssyjnm