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Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders
2014 IEEE Computer Society Annual Symposium on VLSI
Selecting an appropriate estimation method for a given technology and design is of crucial interest as the estimations guide future project and design decisions. The accuracy of the estimations of area, timing, and power (metrics of interest) depends on the phase of the design flow and the fidelity of the models. In this research, we use design space exploration of low-power adders as a case study for comparative analysis of two estimation flows: Physical layout Aware Synthesis (PAS) and Placedoi:10.1109/isvlsi.2014.14 dblp:conf/isvlsi/RatkovicPSUCV14 fatcat:cf6uc5mh3vhjnimnoyw2ev4f6e