Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders

Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Unsal, Adrian Cristal, Mateo Valero
2014 2014 IEEE Computer Society Annual Symposium on VLSI  
Selecting an appropriate estimation method for a given technology and design is of crucial interest as the estimations guide future project and design decisions. The accuracy of the estimations of area, timing, and power (metrics of interest) depends on the phase of the design flow and the fidelity of the models. In this research, we use design space exploration of low-power adders as a case study for comparative analysis of two estimation flows: Physical layout Aware Synthesis (PAS) and Place
more » ... nd Route (PnR). We study and compare post-PAS and post-PnR estimations of the metrics of interest and the impact of various design parameters and input switching activity factor (αI). Adders are particularly interesting for this study because they are fundamental microprocessor units, and their design involves many parameters that create a vast design space. We show cases when the post-PAS and post-PnR estimations could lead to different design decisions, especially from a low-power designer point of view. Our experiments reveal that post-PAS results underestimate the side-effects of clock-gating, pipelining, and extensive timing optimizations compared to post-PnR results. We also observe that PnR estimation flow sometimes reports counterintuitive results
doi:10.1109/isvlsi.2014.14 dblp:conf/isvlsi/RatkovicPSUCV14 fatcat:cf6uc5mh3vhjnimnoyw2ev4f6e