Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning

M. Jun, E.-Y. Chung
2010 Computer journal  
This paper proposes an efficient topology synthesis method for on-chip interconnection network based on crossbar switches. The efficiency of topology synthesis methods is often measured by two metrics-the quality of the synthesized topology and synthesis time. These two metrics are critically determined by the definition of the topology design space and the exploration method. Furthermore, an efficient representing method for the design space is required to tightly link the design space and the
more » ... exploration method. Even though topology synthesis methods have actively been researched, most of the previous methods were not deep in thought for these factors. Unlike the previous methods, we propose a topology synthesis method with a careful consideration of these factors. Our method efficiently defines the design space by a technique called chained edge partitioning, in conjunction with a representing method for the points in the space, called enhanced restricted growth function. We also provide an exploration method which well incorporates with the aforementioned search space. To prove the effectiveness of our method, we compared our method with previous methods. The experimental results show that our method outperforms the compared methods by up to 49.8% and 104.6× in the quality of the synthesized topology and the synthesis time, respectively. Design of On-Chip Crossbar Network Topology Using CEP 905 systems and the other is for application-specific multi-core systems. The former basically concerns on the flow control, routing scheme and other design parameters (e.g. buffer size), while adopting the regular topology such as mesh and torus. This architecture is typically called chip-multi-processor (CMP) architecture. On the other hand, the latter (most of embedded MPSoCs are in this class) even concerns on the network topology, since the area and power costs of an on-chip interconnection network are non-marginal. It is well known that the topology of an on-chip interconnection network largely determines these metrics. Compared with the CMP architecture, there are potential opportunities in optimizing (or customizing) the topology of the application-specific on-chip network for area and power by utilizing the following properties: (i) it is application-or domain-specific (i.e. it targets a limited set of applications), (ii) the traffic pattern among the cores and memories are not symmetric and (iii) the computing cores are heterogeneous (some of them are hardware accelerators) and have realtime constraints. By exploiting the aforementioned properties, it is possible to create custom-tailored irregular on-chip interconnection networks that are more cost-effective than the regular ones. Due to the above reason, optimizing (or customizing) the on-chip network topology has become a critical design step of modern embedded MPSoCs. Recently, several works proposed a cascaded crossbar switch architecture and the corresponding topology synthesis methods in [6] [7] [8] . In this architecture, a single large central crossbar (or partial-crossbar) switch is replaced by multiple smaller crossbar switches which are connected in a cascaded fashion. Figure 1 contrasts the single partial crossbar switch network and the cascaded crossbar switch network with irregular topology. The white rectangles denoted by 'M' are master units (e.g. CPU) and those denoted by 'S' are slave units (e.g. memory). Also, the gray rectangles with inner connections are crossbar switches. A critical problem in this architecture is to find an optimal topology which pays the minimum cost (area, power consumption or both) compared with other possible choices, while satisfying the given communication constraints (bandwidth and latency). It is challenging since there are huge possible topological choices for a given specification. This is the motivation of the topology synthesis of the cascaded crossbar switch network which automatically determines the connections among the master units and slave units by the appropriate selections and connections of crossbar switches. It has been shown that the cost and the performance of a design critically depends on the quality of the topology synthesis methods [6] [7] [8] . Many custom topology synthesis methods for network-onchip have been proposed in [9] [10] [11] [12] [13] [14] [15] . These works usually assume peer-to-peer communication and packet-switched network, while the cascaded crossbar networks assume master-slave communication and circuit-switching. Even though their natures are somewhat different from each other, their topology synthesis problems are quite similar in the sense that they are both to determine the connections among the IPs and switches.
doi:10.1093/comjnl/bxq020 fatcat:6ogxzeviknaobi5l55y2zeg7gu