ISSCC 2019 Session 20 Overview: Noise-Shaped and VCO-Based ADCs

2019 2019 IEEE International Solid- State Circuits Conference - (ISSCC)  
Subcommittee Chair: Michael Flynn, University of Michigan, Ann Arbor, MI Noise-shaping and VCO-based ADCs have been an area of continued interest in the data converter community. This session features 7 designs using these techniques, with bandwidths ranging from 25MHz to 2.5GHz and SNDRs from 45.2dB to 76.6dB, highlighting the wide applicability of these techniques. This session also marks the first 7nm ADC published at ISSCC. In Paper 20.2, MediaTek demonstrates a technique for passive
more » ... for passive signal-residue summation in a noise-shaping SAR ADC in 14nm FinFET technology. It achieves 66.6dB SNDR in a 40MHz bandwidth consuming 1.25mW of power. 9:30 AM 20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4 th -Order Noise-Shaping SAR ADC L. Jie, University of Michigan, Ann Arbor, MI In Paper 20.3, the University of Michigan shows how time-interleaving can be combined with noise-shaping for the first time-interleaved noise-shaping SAR ADC. Implemented in 40nm CMOS, the design achieves 70.4dB SNDR in a 50MHz bandwidth while sampling at 400MS/s and consuming 13mW.
doi:10.1109/isscc.2019.8662345 fatcat:qoarrblqfffw5egd2bplsdu7nu