A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is
2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference
The increasing complexity of system-on-chip design and shorter time to market constraints has stimulated systems designers to investigate performance characteristics of the final system implementation in the early design stages, by means of modeling the design at a high level of abstraction. This paper presents the virtual node concept for modeling the shared resources of a system-on-chip, therefore specifically dedicated to the study of the impact of shared resources contention on the overalldoi:10.1109/newcas.2009.5290506 fatcat:7afn4pjfkra3temhp7dru2idfi