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A systolic processor for signal processing
1982
Proceedings of the June 7-10, 1982, national computer conference on - AFIPS '82
A systolic array is a natural architecture for a high-performance signal processor, in part because of the extensive use of inner-product operations in signal processing. The modularity and simple interconnection of systolic arrays promise to simplify the development of cost-effective, high-performance, special-purpose processors. ESL Incorporated has built a proof of concept model of a systolic processor. It is flexible enough to permit experimentation with a variety of algorithms and
doi:10.1145/1500774.1500801
dblp:conf/afips/FrankGK82
fatcat:dlcqjockobhcdoyg4vwkeb7puu