In order to investigate the effectiveness of small through-silicon vias (TSVs) (diameter 6 μm and depth 21 μm) formed by via-last process using notchless Si etching and wet cleaning of the first metal layer, we fabricated and stacked a thin chip with an array (76 × 500) of small TSVs. Warpage of the thin chip was suppressed by introducing electrostatic chuck stage and head, and the thin chip was stacked without damage to the TSVs and Si region by using soft material (Cu-Ni-solder) bump and

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... rming chip stacking at low temperature and under low pressing load. In addition, we performed 4-terminal and daisy chain measurements on the stacked chips. Our experiments confirmed that the multilayer wiring + TSV + bump connection exhibited low resistance, and the daisy chain was perfectly connected up to 38,000 TSVs.