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Development of a bypass parallel processing block is one of the emerging and interesting research areas in memory read/write application domain. Many Random Number Generation (RNG) techniques have been introduced for processing the data in storage memory. But the limitations include reduced efficiency, increased computational complexity, high area consumption and higher cost. This paper presents a novel dynamic memory register with optimal XOR design based on partial pseudo-random hashing todoi:10.33640/2405-609x.3223 fatcat:i2balt5mzfgfngn4wwc3m7gr7q