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Transient or soft errors are an increasing problem in mainstream microelectronics. We propose a framework for modeling transient-error tolerance (TET) in logic circuits. We classify transient errors as critical or non-critical according to their impact on circuit behavior, such as their ability to disturb the internal state for specified periods of time. We introduce a metric called the critical soft-error rate (CSER) as an alternative to conventional SER, and present some analysis strategiesdoi:10.1109/vts.2007.13 dblp:conf/vts/HayesPB07 fatcat:6rrqbtxzifaw5insbma6zvdnn4