Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube

Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini
2017 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), offers major opportunities for revisiting near-memory computation and gives new hope to mitigate the power and performance losses caused by the "memory wall". In this paper we present the first exploration steps towards design of the Smart Memory Cube (SMC), a new Processor-in-Memory (PIM) architecture that enhances the capabilities of the logic-base (LoB) in HMC. An accurate simulation
more » ... has been developed, along with a full featured software stack. All offloading and dynamic overheads caused by the operating system, cache coherence, and memory management are considered, as well. Benchmarking results demonstrate up to 2X performance improvement in comparison with the host SoC, and around 1.5X against a similar host-side accelerator. Moreover, by scaling down the voltage and frequency of PIM's processor it is possible to reduce energy by around 70% and 55% in comparison with the host and the accelerator, respectively.
doi:10.1109/tvlsi.2016.2570283 fatcat:y5e5bddh7fhljdbsxwmkjl73qa