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Comparative Analysis of Low Power Sequential Elements
2013
International Journal of Computer Applications
Main constraint for any VLSI system is power, speed and area but power consumption is major hurdle for system performance. In this paper a series of improved power efficient sequential elements (flip-flops) are presented. Such as conditional data mapping flip-flop (CDMFF), clocked pair shared flip-flop (CPSFF) and new proposed flip-flop in which dual edge triggered technique is used. In conditional data mapping methodology the less power consumption achieved by mapping the inputs in such way
doi:10.5120/13955-1919
fatcat:euhh2v6wvfhpxfayabkcybxgya