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<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qfrbo4m6rzdebheg6mg47klxcy" style="color: black;">2008 International Conference on Information Processing in Sensor Networks (ipsn 2008)</a>
The rising complexity of data processing algorithms in sensor networks combined with their severely limited computing power necessitates a in-depth understanding of their temporal behavior. However, today only cycle accurate emulation and test-beds provide a detailed and accurate insight into the temporal behavior of sensor networks. In this paper we introduce fine grained, automated instrumentation of simulation models with cycle counts derived from sensor nodes and application binaries to<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ipsn.2008.31">doi:10.1109/ipsn.2008.31</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/ipsn/LandsiedelAW08.html">dblp:conf/ipsn/LandsiedelAW08</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/cvqtwznodfh3lfhtbrsab46s3i">fatcat:cvqtwznodfh3lfhtbrsab46s3i</a> </span>
more »... ide detailed timing information. The presented approach bridges the gap between scalable but abstracting simulation and cycle accurate emulation for sensor network evaluation. By mapping device-specific code with simulation models, we can derive the time and duration a certain code line takes to get executed on a sensor node. Hence, eliminating the need to use expensive instruction-level emulators with limited speed and restricted scalability. Furthermore, the proposed design is not bound to a specific hardware platform, a major advantage compared to existing emulators. Our evaluation shows that the proposed technique achieves a timing accuracy of 99% compared to emulation while adding only a small overhead. Concluding, it combines essential properties like accuracy, speed and scalability on a single simulation platform.
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