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Resistors layout for enhancing yield of R-2R DACs
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
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A new strategy for allocating area, at layout, for enhancing the soft yield of R-2R ladders is introduced. In contrast to the conventional and convenient approach of allocating equal area to each R/2R bit-slice, the new strategy allocates progressively larger areas to higher-order bits. With this strategy, the INL yield for a fixed total resistor area as determined by local random variations in the sheet resistance is optimized. Simulation results show that the new area allocation strategy
doi:10.1109/iscas.2002.1010649
dblp:conf/iscas/LinG02
fatcat:w25jpy6cb5dupch6e3f7kjooka