A 20-Gb/s clock and data recovery circuit incorporates injection-locking technique to achieve high-speed operation with low power dissipation. The circuit creates spectral line at the frequency of data rate and injection-locks two cascaded LC oscillators. A frequency-monitoring mechanism is employed to ensure a close matching between the VCO natural frequency and data rate. Fabricated in 90-nm CMOS technology, this circuit achieves a bit error rate of less than 10 9 in both continuous (PRBS of

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... 31 1) and burst modes while consuming 175 mW from a 1.5-V supply. Index Terms-Burst mode, clock and data recovery (CDR), operational amplifier, phase-locked loop (PLL), injection-locked, voltage-controlled oscillator (VCO).