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This paper proposes a hardware mechanism for reducing coherency overhead occurring in scientific computations within DSM systems. A first phase aims at detecting, in the address space regular patterns (called streams) of coherency events (such as requests for exclusive, shared or invalidation). Once a stream is detected at a loop level, regularity of data access can be exploited at the loop level (spatial locality) but also between loops (temporal locality). We present a hardware mechanismdoi:10.1109/sc.2000.10037 dblp:conf/sc/AcquavivaJ00 fatcat:qzsqb3s2uvc4zic63zpdrjtel4