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In Multicore Network-on-Chip, it is preferable to realize distributed but shared memory (DSM) in order to reuse the huge amount of legacy code. Within DSM systems, memory consistency is a critical issue since it affects not only performance but also the correctness of programs. In this paper, we investigate the scalability of the weak consistency model, which may be implemented using the concept of a transaction counter. Our experimental results compare synchronization latencies for variousdoi:10.1109/iscas.2010.5537833 dblp:conf/iscas/NaeemCLJ10 fatcat:edra5r4m2bbtnbo6ho7qapyjze