Large-scale packet classification on FPGA

Shijie Zhou, Yun R. Qu, Viktor K. Prasanna
2015 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)  
Packet classification is a key network function enabling a variety of network applications, such as network security, Quality of Service (QoS) routing, and other value-added services. Routers perform packet classification based on a predefined rule set. Packet classification faces two challenges: (1) the data rate of the network traffic keeps increasing, and (2) the size of the rule sets are becoming very large. In this paper, we propose an FPGA-based packet classification engine for large rule
more » ... sets. We present a decomposition-based approach, where each field of the packet header is searched separately. Then we merge the partial search results from all the fields using a merging network. Experimental results show that our design can achieve a throughput of 147 Million Packets Per Second (MPPS), while supporting upto 256 K rules on a state-of-the-art FPGA. Compared to the prior works on FPGA or multi-core processors, our design demonstrates significant performance improvements. 978-1-4799-1925-3/15/$31.00
doi:10.1109/asap.2015.7245738 dblp:conf/asap/ZhouQP15 fatcat:uejcag6upzahdcouolrppcodwm