Limitations of the High–Low $C$ –$V$ Technique for MOS Interfaces With Large Time Constant Dispersion

Ashish Verma Penumatcha, Steven Swandono, James A. Cooper
2013 IEEE Transactions on Electron Devices  
We discuss the limitations of the high-low CV technique in evaluating the interface trap density (D IT ) in MOS samples with a large time constant dispersion, as occurs in silicon carbide (SiC). We show that the high-low technique can seriously underestimate D IT for samples with large time constant dispersion, even if elevated temperatures are used to extend the range of validity. Index Terms-AC conductance technique, interface states, interface traps, silicon carbide (SiC), wide-bandgap semiconductor.
doi:10.1109/ted.2013.2237777 fatcat:2kcjw6ukofdrxpmwf4brp5zfya