A hardware implementation of genetic algorithms for measurement characterization

M.S. Sharawi, J. Quinlan, H.S. Abdel-Aty-Zohdy
9th International Conference on Electronics, Circuits and Systems  
Integrated circuits that sense, receive, transmit, and process signals are the eye, ears, and nose of the biotechnical field of the millennium. To process/store/analyze signals acquired from sensors, hybrid systems with flexible and adaptable Intelligent Information Processing and Perception (IIPP) are needed. Genetic Algorithms (GA) present a suitable pre-processing operation because of their good convergence to optimum solutions. Most of GAs are built via software because of their ease of
more » ... ing and customization. Less attention has been given to hardware implementation of such algorithms. In this paper we present a hardware design approach of a GA for optimum measurements representation to a following IIPP stage. A multilevel verification of the GA is performed via VHDL. In particular the design of efficient universal multipliers and dividers is addressed. A new timing efficient approach for Crossover that is based on least error value is proposed. The Crossover scheme is called Half Siblings and a Clone. Such a scheme needs 10 iterations to converge to the optimum result in the system proposed for sensor measurement optimization. This takes 7680 clock cycles, which is only 96 µsec when implemented in the 0.25 µm CMOS technology. 1
doi:10.1109/icecs.2002.1046485 fatcat:wgbzbxuumngerkkpgyj4rg5dua