A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is
A 4GHz 3 rd order continuous-time ∆Σ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45nm-LP CMOS and achieves 70dB DR and −74dBFS THD in a 125MHz BW, while dissipating 260mW from 1.1/1.8V supply. The ADC occupies 0.9mm 2 including the modulator, clock circuitry and decimation filter.doi:10.1109/jssc.2011.2164963 fatcat:rqy2majoznbznepsuii63zat3y