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An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD
2015 IEEE International Symposium on Multiple-Valued Logic
This paper proposes an FFT circuit based on a residue number system (RNS) using LUT cascades. To reduce the number of look-up tables (LUTs) in an FPGA, we used two techniques. The first one is the functional decomposition of multipliers using RNS. The second one is the increase of the dynamic range stage by stage. The circuit requires the RNS2RNS converter which converts a small dynamic range to a large dynamic range. To compactly realize the RNS2RNS converter, we decompose it into andoi:10.1109/ismvl.2015.41 dblp:conf/ismvl/NakaharaSNI15 fatcat:hv5cn6jjnfgkhmv5d6yexycsf4