An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD

Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai
2015 2015 IEEE International Symposium on Multiple-Valued Logic  
This paper proposes an FFT circuit based on a residue number system (RNS) using LUT cascades. To reduce the number of look-up tables (LUTs) in an FPGA, we used two techniques. The first one is the functional decomposition of multipliers using RNS. The second one is the increase of the dynamic range stage by stage. The circuit requires the RNS2RNS converter which converts a small dynamic range to a large dynamic range. To compactly realize the RNS2RNS converter, we decompose it into an
more » ... converter and a Binary2RNS converter. Although the Binary2RNS converter can be realized by an LUT cascade based on a multi-terminal multi-valued decision diagram (MTMDD), the RNS2Binary converter tend to be large for the conventional circuit. Thus, we introduce an LUT cascade based on a modulo edge-valued multi-valued decision diagram (mod-EVMDD). The mod-EVMDD is a new type of a decision diagram that efficiently represents the RNS2Binary converter. We implemented the proposed RNS FFT on the Xilinx Corp. Virtex 6 FPGA. Compared with the conventional binary FFT implementation, although the number of block RAMs (BRAMs) increased by 11.1-25.0%, the number of LUTs decreased by 44.2-52.2% and the maximum clock frequency increased by 9.3-41.7%. With this technique, we successfully implemented a required FFT on an available FPGA, since the excessive number of LUTs was the bottleneck of the binary FFT.
doi:10.1109/ismvl.2015.41 dblp:conf/ismvl/NakaharaSNI15 fatcat:hv5cn6jjnfgkhmv5d6yexycsf4