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A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design
Single event double upsets (SEDUs) caused by charge sharing have been an important contributor to the soft error in integrated circuits. Most of the up-to-date double-upset (DU) tolerant latches suffer from high costs in terms of delay, power and area. In this paper, we propose a novel high-performance low-cost double-upset tolerant (HLDUT) latch. Simulation waveforms have validated the double-upset tolerance of the proposed latch. Besides, detailed comparisons demonstrate that our design savesdoi:10.3390/electronics7100247 fatcat:xcar2cpq5naw3fcrjz4gbnbfse