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With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs, especially for high-performance ICs. Usually having level-sensitive latches for their speed, high-performance IC designs need to verify the clock schedules. With process variations, the verification needs to compute the probability of correct clocking. Because of complex statistical correlations, traditional iterative approaches are difficult to get accurate results.doi:10.1109/iccad.2004.1382650 dblp:conf/iccad/ChenZ04a fatcat:2hscmhygcjac5lgszbv73j2byi