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The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC. The novel feature of the approach is the use an embedded microprocessor memory pair to test the remaining components of the SOC. Test data is downloaded using DMA techniques directly into memory while the microprocessor uses the test data to test the core. The test results are tranferred to a MISR for evaluation. The approach has several important advantages overdoi:10.1145/309847.310004 dblp:conf/dac/PapachristouMN99 fatcat:7en4kesjsrdq7hzlmyu3wappyq