Raj Arya, Bala Tripura, Sundari
2016 unpublished
A scaled down graphene field effect transistor (GFET) has been modeled by incorporating the quantum capacitance effects. The proposed GFET model scaled down to 90nm has been developed using compact model equations. Metal oxide gated compact GFET models have been modeled without considering variation of top gate capacitance with quantum capacitance effects. But the effects of deviation of quantum capacitance become more with scaling down and cannot be neglected. In this paper the compact drain
more » ... rrent equation has been derived by incorporating the dependence of quantum capacitance on the channel voltage and on intrinsic parameters of the device has been considered. The parameters of interest for circuit design have been determined from current characteristics, transfer characteristics, trans-conductance, and transit frequency. As the measure of performance of the model library in a circuit is often defined as unit gate delay, we propose to determine the rise time and fall time of a single GFET inverter and present the results. Keywords: graphene field effect transistor, quantum capacitance, small signal model, large signal model. INTRODUCTION The scaling of silicon has reached its physical limit and hence non silicon based devices are the key. Carrier mobility of graphene is much higher than silicon which makes it a promising material for field effect transistors (FETs). During last few years, graphene field effect transistors (GFETs) are successfully modeled and they exhibit outstanding I-V characteristics suitable for RF applications. Many compact models using ballistic and drift diffusion approach exist today [1]-[3],[5]-[8].Electrolytic gated GFET model in [2] incorporates effects of quantum capacitance and the graphene-electrolyte interface of graphene. But the drain current equations of metal oxide gated GFETs [1], [3] have been derived without considering the variation in top gate capacitance due to quantum capacitance effects. But these effects become prominent in short channel transistors [4]. This model is a drift diffusion based model developed in 90nm technology where variation in top gate capacitance due to quantum capacitance effects has been taken into account. The focus here is on the development of a compact model using closed form expression for individual graphene transistors at 90nm scale based on drift diffusion approach to determine drain current, trans-conductance and transit frequency. Compact model of 100 nm using drift diffusion is available [3]. The 90nm model incorporates quantum capacitance effects with a compatibility of being used in future circuit applications within a design environment and an analog mixed signal library of it has been developed by verifying the model in HSPICE. This paper is organized as follows: Section II discusses the quantum capacitance and how to incorporate this into the model. Section III presents the formulation of the compact model for GFETs and Section IV presents the results and section V gives the conclusion.