Worst-case circuit delay taking into account power supply variations

Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low or high. This analysis may not give the true maximum delay of a circuit because it neglects the possible mismatch between drivers and loads. We propose a new approach for timing analysis in which we first identify the critical path(s) of a circuit using a power-supply-aware timing model. Given these critical paths, we
more » ... ritical paths, we then take into account how the power nodes of the gates on the critical path are connected to the power grid, and re-analyze for the worst-case time delay. This re-analysis is posed as an optimization problem where the complete operation of the entire circuit is abstracted in terms of current constraints. We present our technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids.
doi:10.1145/996566.996745 dblp:conf/dac/KouroussisAN04 fatcat:detstqp4znexhgwosctuwrf6z4