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In this paper, a high-speed PLA based on latch sense amplifiers and a charge sharing scheme is presented. The circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By latch sense amplifiers, a read-out scheme sensing the differential voltage of dual-rail bit-lines caused by charge sharing is used for high-speed operation. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly,doi:10.1145/370155.370195 dblp:conf/aspdac/YamaokaIA01 fatcat:alylhigjqbbyljgzwoo5gjjo4q