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VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
Testing of interconnects on a printed circuit board has been studied and the procedure has been standardized in the IEEE 1149.1 (JTAG) standard. The Sysem-on-Chip (SOC) technology allows us to integrate on the same chip, most of the electronics on a PCB. However, since an SOC operates at a much higher speed and has a very large packaging density, testing its interconnects is different. For example, one must address the crosstalk faults with chip-level interconnects. Not much literature existsdoi:10.1109/icvd.2000.812638 fatcat:ym37x36qdzbvbokmkobfjgr72e