Low maintenance verification
Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06
Guaranteeing the functional correctness of a digital integrated circuit is an unfulfilled challenge for even the most straightforward practical designs. The reality for even the simplest of today's designs is that they are released with latent bugs. Some of these bugs are innocuous, others are simply annoying, but still others are potentially dangerous to the users of the system or they might compromise its security, or adversely affect its performance. While the past few decades have witnessed
... significant efforts to improve verification methodology for hardware systems, these efforts have been far outstripped by the massive complexity of modern digital designs, to the point that today only a vanishingly small fraction of a design's possible behavior is verified to be correct before the manufactured system is delivered to the end user. Looking forward, the rise of highly complex chip-multiprocessors and heterogeneous systems-on-a-chip is deemed to only exacerbate this problem to new heights. It seems a reasonable prediction to say that, without out-of-the-box new thinking in verification research, it is only a matter of time before an escaped design error becomes the cause of a broad impact incident, perhaps worse than the Intel FDIV bug disaster of the mid 1990's. In this paper we present ideas to attack this problem from two opposite directions: on one hand, we present solutions which boost the coverage of design-time verification technologies, through closed-loop, hybrid semi-formal verification technologies. On the other hand, we provide techniques to craft novel hardware mechanisms which permit to deftly circumvent escaped bugs or even correct them after the device has been deployed in the field. Our ultimate vision for these technologies is to make hardware as malleable as software.