Queue management for QoS provision build on network processor
The Ninth IEEE Workshop on Future Trends of Distributed Computing Systems, 2003. FTDCS 2003. Proceedings.
Network processor is a kind of programmable processor performing network computing with special design and optimization. To some extent, it can be viewed as a tight-coupled multi-processor system due to its architecture of multiple in-chip processors, buses and other key components. Network processor has the property of combination of the flexibility of software and the high performance of hardware. The design and development of networking systems using network processors is an emerging field
... an emerging field that offers numerous challenges and opportunities. This paper provides the design and implementation of queue management module combining buffer management and packet scheduling for QoS provision that uses Intel's network processor and follows the relative differentiated service model. The architecture, the processing diagram, especially some key design issues such as the system synchronization and the system resource management are discussed in detail. There're four kinds of storage components in IXP1200, and have different usage according to their properties. Register: Its access speed is the fastest and capacity is the smallest. It can be used for the communication between contexts in a MicroEngine, and temporary variable data, etc. Scratchpad: faster and bigger, for the communication between MicroEngines, temporary processing results, and error records, etc. SRAM: faster and bigger much more, for route lookup table, packet descriptors, queue descriptors, communication between MicroEngines, and communication between MicroEngines and StrongARM, etc. DRAM: slowest and biggest, for storage of route forwarding table information and packet payload, etc.