Platform-based design faces an essential tension: it wants to reuse previous designs to leverage IP; but new designs must necessarily include work that is not complete or well-characterized. Synthesis and analysis methods are therefore important elements in platform-based design methodologies. This paper describes two aspects of this problem. First, we consider the first-generation dilemma, in which we must use additional analysis in order to create the first generation of a platform. Second,

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... describe a synthesis method that creates accelerators for platforms whose clock periods have been optimized for the system characteristics. The next section surveys previous work. Section 3 provides some general observations on platform-based design. Section 4 concentrates on design methodologies. Section 5 describes the first-generation dilemma. Section 6 describes our work on the synthesis of accelerators with custom clock rates. Related Work in System-Level Design Tools In a few years, over one billion transistors will be available on a single chip, 1 making systems-on-chips common place. Such ample resource offers cheaper while more functional designs, but these designs are too difficult and expensive for traditional RTL design methodologies. System-level designs are introduced to absorb the growing complexity and accelerate larger designs. They take advantage of IP cores and the idea that right system-level design choices could save much more than right lower level design choices in complex designs. Many system-level design tools were announced in recent years, including CoWare N2C, 2 Cadence VCC (Virtual Component Co-design), Summit Visual Elite, 3 Elanix SystemView, 4 and Synopsys Co-Centric System Studio. 5 Many types of system-level design tools have been developed. Modeling languages and simulation systems allow system designs to be described at a relatively high level of detail. Interface synthesis tools create hardware and software interfaces between components such as software running on microprocessors and I/O devices. Synthesis tools have been developed for specialized design domains such as signal processing and reactive systems. Hardware/software co-synthesis 6 is the process of designing the hardware and software modules to meet performance, power and cost goals for an embedded system. The output of a co-synthesis tool is a cost-minimal distributed computing system that meets all system specification and constraints. There is a great deal of previous work in hardware/software co-synthesis. 6-8 Hardware/software partitioning algorithms were the first type of co-synthesis algorithm. They implement the system specification on some sort of architectural template, usually a single CPU with one or more ASICs connected to the bus. Distributed system co-synthesis does not use an architectural template to drive co-synthesis. Instead, it creates a multiprocessor architecture for the hardware engine. The target architecture is usually heterogeneous in both its processing elements and its communication channels. It can employ multiple CPUs, ASICs and FPGAs. The SOS system, 9 which was the first hardware/software co-synthesis method, is an exact method that uses mixed integer linear programming technique (MILP). They reported CPU times exceeding 10 000 CPU seconds for small examples. However, optimal approaches are suitable only for small task graphs and impractical. As a result, most researchers use heuristics to find a solution quickly and efficiently. There are two distinct approaches in the heuristic domain: iterative and constructive. The iterative approach begins with an initial solution and improves it. 7,10 A