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Thermomechanical Stress-Aware Management for 3D IC Designs
2013
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
The thermomechanical stress has been considered as one of the most challenging problems in three-dimensional integration circuits (3D ICs), due to the thermal expansion coefficient mismatch between the through-silicon vias (TSVs) and silicon substrate, and the presence of elevated thermal gradients. To address the stress issue, we propose a thorough solution that combines design-time and run-time techniques for the relief of thermomechanical stress and the associated reliability issues. A
doi:10.7873/date.2013.260
dblp:conf/date/ZouZKX13
fatcat:yubjew7v35h73mpl2lvhvcqwkm