Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. Network-on-Chip (NoC) structures have been proposed as a solution to achieve efficient and reliable communication. Even with the regularity of NoC structures, it is important for designers to acknowledge the physical layer interconnect issues to plan and quantify achievable performance. In this paper we present a spice-based tool: No-CIC: Network-on-Chip Interconnect

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... ulator, which enables NoC designers to assess the impact of interconnect circuit designs and understand the tradeoffs involved to achieve better a priori interconnect planning. NoCIC determines the interconnect performance and power based on select NoC and circuit parameters. The effects of each parameter on the interconnect performance and power are expressed through various two-dimensional and three-dimensional plots.