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Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. Network-on-Chip (NoC) structures have been proposed as a solution to achieve efficient and reliable communication. Even with the regularity of NoC structures, it is important for designers to acknowledge the physical layer interconnect issues to plan and quantify achievable performance. In this paper we present a spice-based tool: No-CIC: Network-on-Chip Interconnectdoi:10.1145/966747.966762 dblp:conf/slip/VenkatramanLJKZB04 fatcat:62d6q5kqt5btvk7rxhozdmu4za