Architecture of BIST for Memory Testing

Diksha V.M
2019 International Journal for Research in Applied Science and Engineering Technology  
Memories are the most essential component in all storage devices. Memory structure become complex when it is upgrading. Due to higher level of integration in memory size, manufacturing cost of the device is reducing and testing cost is increasing. Testing is needed to give the fault free products. Large number of bit pattern requires more time to test the circuit. Test algorithms are necessary to minimize the testing time. In this paper, the memory built-in self-test mechanism is represented
more » ... enhancing the functionality of the memory. The main motive behind the use of this technique is to smooth the progress of the memory for self-test. This is achieved with the help of an advanced method known as Built-in self-test architecture, March algorithm is also been utilized for the proficient fault coverage. The main intent of this paper is to reduce the whole test time and improve the yield by considering the economic circumstances as well.
doi:10.22214/ijraset.2019.9146 fatcat:5fqkgh7665g5zdw2sbi6da7s3m