Managing leakage for transient data

Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
Much of on-chip storage is devoted to transient, often short-lived, data. Despite this, virtually all on-chip array structures use sixtransistor (6T) static RAM cells that store data indefinitely. In this paper we propose the use of quasi-static four-transistor (4T) RAM cells. Quasi-static 4T cells provide both energy and area savings. These cells have no connection to Vdd thus inherently provide decay functionality: values are refreshed upon access but discharge over time without use. This
more » ... s 4T cells uniquely well-suited for predictive structures like branch predictors and BTBs where data integrity is not essential. We use quantitative evaluations (both circuit-level and cycle-level) to explore the design space and quantify the opportunities. Overall, 4T based branch predictors offers 12-33% area savings and 60-80% leakage savings with minimal performance impact. More broadly, this paper presents a different view of how to support transient data in power-aware processors.
doi:10.1145/566408.566423 dblp:conf/islped/HuJDKSMC02 fatcat:nec3f7hpo5asdkwfrq5yqy3kmq