A. novel approach to reduce L2 miss latency in shared-memory multiprocessors

M. E. Acacio, J. Gonzalez, J. M. Garcia, J. Duato
2002 Proceedings 16th International Parallel and Distributed Processing Symposium  
Recent technology improvements allow multiprocessor designers to put some key components inside the processor chip, such as the memory controller, the coherence hardware and the network interface/router. In this work we exploit such integration scale, presenting a novel node architecture aimed at reducing the long L2 miss latencies and the memory overhead of using directories that characterize cc-NUMA machines and limit their scalability. Our proposal replaces the traditional directory with a
more » ... vel threelevel directory architecture and adds a small shared data cache to each of the nodes of a multiprocessor system. Due to their small size, the first-level directory and the shared data cache are integrated into the processor chip in every node. A taxonomy of the L2 misses, according to the actions performed by the directory to satisfy them is also presented. Using execution-driven simulations, we show significant L2 miss latency reductions (more than 60% in some cases). These important improvements translate into reductions of more than 30% in the application execution time in some cases.
doi:10.1109/ipdps.2002.1015554 dblp:conf/ipps/AcacioGGD02 fatcat:s4zmex6ezvg5vnghe4py3p5btu