A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
A. novel approach to reduce L2 miss latency in shared-memory multiprocessors
2002
Proceedings 16th International Parallel and Distributed Processing Symposium
Recent technology improvements allow multiprocessor designers to put some key components inside the processor chip, such as the memory controller, the coherence hardware and the network interface/router. In this work we exploit such integration scale, presenting a novel node architecture aimed at reducing the long L2 miss latencies and the memory overhead of using directories that characterize cc-NUMA machines and limit their scalability. Our proposal replaces the traditional directory with a
doi:10.1109/ipdps.2002.1015554
dblp:conf/ipps/AcacioGGD02
fatcat:s4zmex6ezvg5vnghe4py3p5btu