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Fermilab Physics Department Fastbus TDC Module
1990 IEEE Nuclear Science Symposium Conference Record
A prototype 64 channel Fastbus TDC built at Fermilab is described The module features a full custom CMOS fom chatmel gad integnuu chip. one level of analog buffering at the inputs is impkmented cm chip. A four event dce.p output queue at the bus interface allows * bigb event rate with low dead time. Each channel can record up to hvo hits per event With an occupation rate of 10%. the module can opcmtc at 40,ooO events per seccd with dead time on the order of 15%.
doi:10.1109/nssmic.1990.693341
fatcat:kfpyznpy6ndbja5z2yqqlca4t4