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2009 IEEE Energy Conversion Congress and Exposition
This document presents a method to optimize integrated LDMOS transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout vs. loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50 MHz converter, resulting in a 35% reduction in power lossdoi:10.1109/ecce.2009.5316121 fatcat:py4uxlssxzardnbofmsjsyqtqy