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The formal verification has become a recommended practice in safety-critical software engineering. The hand-written of the formal specification requires a formal expertise and may become complex especially with large systems. In such context, the automatic generation of the formal specification seems helpful and rewarding, particularly for reused and generic mapping such as hardware representations and real-time features. In this paper, we aim to formally verify real-time systems designed bydoi:10.1145/3167132.3167282 dblp:conf/sac/MkaouarZHJ18 fatcat:pif5pc7fjnhhjicuyvxtge2kb4