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HSP16: A Hardware Simulator for Pesona 16
2002
Jurnal Teknologi
Hardware Simulator for Pesona 16 (HSP16) is a simulated environment of the Pesona-16 microprocessor for execution of the host-code to enable parallel co-design and co-verification. The simulator core is a typical Instruction Set Simulation (ISS) model, also called Register Transfer Level (RTL) that incorporate an instruction simulation, debugging facility and devices interfacing. The simulator is developed with C and is capable of replacing the real hardware and are fully modularised.
doi:10.11113/jt.v36.577
fatcat:xlefqskg5jam5f7dv436uiga5e